Modern circuit designs are typically specified programmatically using a hardware description language (HDL). In order to implement the HDL design within an integrated circuit (IC), an electronic design automation (EDA) system processes the HDL design through a design flow. The design flow typically includes multiple stages such as synthesis, which generates a netlist from the HDL design, technology mapping, placement, and routing. In some cases, the design flow may also include generation of a configuration bitstream.
When processing the circuit design through a design flow, the EDA system attempts to perform a variety of different optimization techniques on the circuit design. Often, these optimization techniques are timing-dependent. For example, whether an operation is performed and, if performed, how the operation is performed, usually depends upon current timing estimates for the circuit design and/or particular timing paths. In the usual case, the timing estimates are determined using static timing analysis techniques.
Performing the operations serially can significantly increase runtime of the EDA system. Since the timing-dependent operations tend to be global in nature, parallelizing the operations is a complex and difficult task.